The invention relates to a circuit arrangement for noise suppression in binary data signals in a digital transmission system.
A plurality of digital transmission systems for a great variety of uses are known wherein the data in the form of binary signals are transmitted on the basis of one or more rigidly prescribed nominal bit clock frequencies. Produced by a great variety of causes, malfunctions can occur on the communication link, whereby high-frequency noise components superimpose on the transmitted data signals.
For example, a data processing system with digitally functioning magnetic tape recorder means as peripheral memories represents an example of such a data transmission system. In this use situation, malfunctions are attributed to the fact that, for example, dirty or worn tape material, or dirty or worn heads for recording are employed. The typical fault pattern in read signals of magnetic tape stores is based on a collapse of or glitch in the read signal amplitude in the region of an edge change, so that multiple edges then appear instead of a single signal edge. Such devices, moreover, also work with a high recording density and, given the high resolution of the system comprising the magnetic head and magnetic layer then required, brief noise pulses in the digitized read signal can also appear between more remote pulse edges.
The possibility is fundamentally available of eliminating such high-frequency malfunctions by techniques which take effect either in the frequency range or in the time range. To be included in the former form of noise suppression are all those known techniques wherein the more or less worn edges of the data signals are converted into optimally pronounced rectangular pulses with the assistance of passive filters and pulse shaping networks. However, limits are placed on the use of passive filters because distortions which are unavoidable are particularly unpleasant, especially in the aforementioned use situation since no clock is transmitted in addition to the data signals, but must first be recovered from the data signals. It is thus particularly critical that the nominal period for a bit cell can likewise fluctuate because of an allowable deviation of the momentary tape speed for the nominal value.
It is therefore frequently preferred to execute the noise suppression by means of techniques in the time range. The apparatuses known for this purpose are based on the fact that noise signal components are of very short duration in comparison to the useful signals. Noise signals are thus discriminated from useful signals on the basis of a significantly shorter pulse duration of the noise components. In other words, an identified edge change is only interpreted as an edge change in the useful signal when the polarity in the binary signal is also maintained after the lapse of a predetermined, short time span. This time span is selected somewhat longer than the duration of the longest possible noise signal.
In a known apparatus for the realization of this principle, the noise-infested binary data signals are supplied to a flip-flop circuit acting as a pulse shaper and are converted into signals having normal and inverted polarity. Each of the pulse trains obtained in such fashion is then further processed in parallel in a separate circuit branch. An integrator is provided in every circuit branch, which is initiated by a positive edge change so as to integrate the following pulse up until the appearance of the next successive negative edge. When a prescribed threshold is exceeded, the integrator emits an output pulse having a corresponding width which, for example, can then be differentiated. The differentiated signals of both circuit branches which are obtained are supplied to the set or reset inputs of a further flip-flop which outputs the noise-deinfested binary data signals at its output.
Obviously, this known circuit arrangement is in a position to effectively suppress faults, i.e. brief polarity changes, lying between remoter, actual edge changes of the binary data signal when the threshold evaluating the integrated data signal is prescribed high enough in order to effect a signal delay which is sure to be adequate for every fault. The behavior of this circuit arrangement, however, is more critical in view of faults of the binary data signal which appear in the region of an actual pulse edge. In every case, it is only the last of these multiple edges which is interpreted as a true edge in the binary data signal. This potentially leads to considerable distortions, and thus to difficulties in the recovery of the nominal bit clock.